1. Field of the Invention
The present invention relates to non-volatile memories. More specifically, the present invention relates to a non-volatile NAND array memory cell structure and a method of manufacturing such memory cell structure.
2. Discussion of the Related Art
A memory cell of a non-volatile memory device, such as electrically programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROMs), has an electrically isolated gate, referred to as a floating gate, on which data is stored in the form of electrical charge. Charge is transported to or removed from the floating gate by program and erase operations.
One type of non-volatile memory allows erasure and reprogramming inside a system, without requiring an additional external power supply. Flash memory devices are typically lower in cost and available in higher densities than conventional EEPROM. As a result, flash memory is well-suited to a number of end-product applications, including existing embedded-system flash applications as personal computers and peripherals, solid state disks, telecommunication switches, cellular phones, and internetworking, instrumentation and automotive devices, and emerging consumer-oriented voice, image and data storage products such as digital still cameras, digital voice recorders, and personal digital assistants (PDAs). A flash memory structure typically consists either NOR or NAND memory cell blocks, depending on the specific application.
In a typical layout of a flash memory, the memory cell blocks contain memory cells arranged in a common region which is referred to as the xe2x80x9ccorexe2x80x9d area of the chip. Other components necessary for operating the flash memory devices, such as block select transistors, charge pumps, etc. are located at the peripheral areas of the chip. In each block, block select transistors select the core floating gate transistors to be operated upon, and typically consist of a select drain transistor and a select source transistor.
FIG. 1 shows a conventional NAND array block which has a series of floating gate transistors Q0 through Q15 coupled in series between a select drain transistor QSD and a select source transistor QSS. Select drain transistor QSD is coupled to bit-line 100 and select source transistor QSS is coupled to an array voltage source providing select source voltage VSS. Select drain transistor QSD selects or deselects bit-line l00 during programming. Each of floating gate transistors Q0 through Q15 is a memory cell that is programmed and erased using Fowler-Nordheim tunneling. Each float gate transistor has a control gate connected to a respective word-line (e.g., word-line WL0 through WL15) and which is
In Fowler-Nordheim tunneling programming, electrons are induced into a floating gate of a selected memory cell (e.g., memory cell Q0) by first turning select source transistor QSS and select drain transistor QSD off to isolate the memory cells (i.e., memory cells Q0 through Q15), biasing the control gate of the selected memory cell at a relatively high voltage of approximately 18-20 volts, and grounding the body region of the selected memory cell. The high voltage on the control gate of the selected memory cell induces electrons from the body region (i.e., the substrate) to tunnel through the lower tunnel oxide layer and into the floating gate. When the floating gate accumulates negative charges, the threshold voltage of the selected memory cell is increased.
In Fowler-Nordheim tunneling erasing, the substrate is biased at approximately 18-20 volts while the control gate is grounded, thus driving the electrons from the floating gate back into the substrate. While programming is typically performed individually to each memory cell, erasing is typically performed to a block of memory cells.
Reprogramming is typically accomplished by block erasure and then programming individual selected memory cells.
The above described Fowler-Nordheim tunneling technique has several drawbacks. For example, two block select transistors are required per string, taking up premium space on the chip. In addition, the conventional memory cell structure described above requires on-chip generation and handling of the 18-20 volts programming voltages. Circuits handling such high voltages are more complex and larger than circuits for lower voltage applications. Furthermore, only one memory cell in each string can be programmed at any time.
The high voltage applied to the word-line during programming has an additional disadvantage. That is, during a write operation to a selected memory cell, the high bit-line and word-line voltages for the selected memory cell can create a large voltage difference between the floating gate and the drain terminal of a nearby unselected memory cell. The large voltage difference induces Fowler-Nordheim tunneling that disturbs the threshold voltages of the unselected memory cell by causing electrons to tunnel out of the floating gate to the drain terminal. This unintended consequence is known in the industry as xe2x80x9cprogram disturb.xe2x80x9d
Program disturb is undesirable because the charge in the drain terminal of an unselected memory cell in the string accumulates each time a different selected memory cell is programmed, so that, after a few write operations, an unselected memory cell may have accumulated enough charge to become a programmed memory cell. In the prior art, an unselected word-line is boosted to the selected line potential (xe2x80x9cself-boostingxe2x80x9d) to diminish the effective voltage across the memory cell. However, to provide self-boosting, additional circuitry is required, adding to cost and device area.
FIG. 2 shows a cross-sectional view of a NAND string. Typically, each memory cell (e.g., floating gate transistor Q15) includes source region 22, drain region 24, channel region 26 and stacked gate structure 28, which is formed separated from channel region 26 by dielectric layer 32. As shown in FIG. 2, within the string, source region 22 is shared as drain region 24 by an adjacent memory cell. In FIG. 2, source region 22 and drain region 24 are N+ type high impurity concentration regions, channel region 26 is a P-type region, and substrate 20 is an N-type substrate.
Stacked gate structure 28 typically includes floating gate 34, formed by a first polysilicon layer (poly I), and control gate 38, formed by a second polysilicon layer (poly II). Floating gate 34 is isolated from control gate 38 by dielectric layer 36 and from channel region 26 by thin dielectric layer 32, which is typically approximately 100 xc3x85 (Angstrom) thick. Thin dielectric layer 32 is commonly referred to as the tunnel oxide. Dielectric layer 36 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) stack. Select source transistor QSS and select drain transistor QSD do not have a stacked gate structure.
The principal electrical measurement of a floating gate transistor, called the xe2x80x9cbetaxe2x80x9d measurement, measures the amplification characteristic of the floating gate transistor. Beta is the ratio of the source-drain current to the gate current. For example, a 1-mA (milliampere) gate current and a 10-mA source current correspond to a beta of 10. Beta is determined by junction depths, junction separation (base width L), doping levels, concentration profiles, and other process and design factors. A beta in the range of 20 to 50 is typically desirable.
The present invention provides a NAND array structure and a method for manufacturing such an array structure that is compact and substantially free of program disturbs.
According to one embodiment of the present invention, a NAND array structure programmable by hot electron injection is provided. In one embodiment, the NAND array structure includes a buried layer formed at a junction between the substrate and a well. The buried layer can be achieved by implanting antimony into a substrate layer, and thereafter, growing an epitaxial layer over the implanted substrate layer. A well is then formed in the epitaxial layer.
A first dielectric layer is then formed over the substrate. A stacked gate structure is then formed over the first dielectric layer. In one embodiment, the stacked gate structure includes a floating gate over the first dielectric layer, a second dielectric layer above the floating gate, and a control gate. In one embodiment, over the control gate is provided, in order, a tungsten-silicide layer, a polysilicon cap and a silicon oxynitride layer.
In one embodiment, a single select source transistor per string is provided for string selection. In that embodiment, the gate structure of the select source transistor is formed from the same layer that formed the floating gate of the memory cells.
In one embodiment, the memory cell is programmed by applying a first voltage (e.g., approximately 4-5 volts) to the bit-line, a second voltage (e.g., ground) to the select source transistor, a third voltage (e.g., approximately 6-10 volts) to a selected word-line and a fourth voltage (e.g., approximately 0-2 volts) to an unselected word-line. In one embodiment, the difference between the third voltage and the fourth voltage is greater than the memory cell""s threshold voltage which, in that embodiment, is approximately 2-3 volts. Prior to programming, all the cells are placed in a known state by block erasure.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.